22 lines
532 B
Makefile
22 lines
532 B
Makefile
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#OBJS specifies which files to compile as part of the project
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OBJS = main.c
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#CC specifies which compiler to use
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CC = clang
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#COMPILER_FLAGS specifies the additional compilation options we're using
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# -w suppress all warnings
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COMPILER_FLAGS = -Wall
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#LINKER_FLAGS specifies the libraries we're linking against
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LINKER_FLAGS =
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#OBJ_NAME specifies the name of our executable
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OBJ_NAME= test
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#This is the target that compiles our executable
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all : $(OBJS)
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$(CC) $(OBJS) $(COMPILER_FLAGS) $(LINKER_FLAGS) -o $(OBJ_NAME)
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clean :
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rm test
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